The present invention relates to a semconductor device which includes a package enclosing at least one semiconductor chip, a method of manufacturing such a semiconductor device and a method of assembling a semiconductor assembly which includes a plurality of packages each comprising a plurality of semiconductor chips. In particular, the present invention relates to the packaging of multi-chip RAM assemblies.
In the semiconductor industry many advances are taking place in packaging different varieties of semiconductor components. Power components and components having high pin count are being provided with new packagings and to a lesser extent packagings for random access memories (RAMs) are also being developed. As RAMs constitute a large proportion of the electronics cost of a system, advances in packaging RAMs are very desirable. Generally, it is desired to build systems that are easy to build, easy to cool and have a high performance per unit volume. The applicant has already developed a microcomputer on a single chip (known as the "Transputer"--Transputer being a Registered Trade Mark of INMOS Limited) which attacks these problems by minimising the amount of "glue" logic needed to interface the processing chips to the memory and peripheral chips. This gives a substantial benefit in terms of processing power per unit volume. An effect of the improvement of this single chip microcomputer development is that the physical size and power consumption of the microcomputer system tends to be dominated by the amount of RAM used in the system. Typically, the microcomputer and glue logic take only 15% of the printed circuit board area, the remainder being taken by the RAM required by the system.
A number of known RAM packages exist. For example it is known to have dual-inline-packages (DIPs), zig-zag-packages (ZIP), surface mount packages (SOIC or SOJ) and the so-called "flip-chip" dies. Particular examples of such packages can achieve a packing density of silicon area over printed circuit board area of above 25%, the density normally achieved only with hybrid packaging techniques which mix thin or thick film and printed circuit technologies.
All of these known packages except for the flip-chip package suffer from the disadvantage that a large amount of area is required by the fan-out of the leads extending from the chips. In addition, RAMs tend to be rectangular chips, with bonding pads at the two ends thereof, whilst the packages tend to have leads along their sides and therefore considerable area is taken up in turning the leads through a right angle. In the flip-chip design, the fan-out from the chip bonding pads takes place within the area of the chip but the disadvantage of this package is that it is not surface-mount and so the package cannot be assembled on both sides of a printed circuit board. Even the existing surface-mount packages are not always ideal for mounting on both sides of a board because they have substantial thickness. The thickness is necessary partly to turn the leads under the body and also partly to give enough thickness of plastics material used for the package to give the package mechanical strength. A so-called "VSOP" single RAM chip has been produced by Mitsubishi which is very small, has short leads on a fine pitch at the ends of the package and is only 1 mm thick. However, the VSOP package is so small that many RAM chips are too large to fit into it. Also, it has such a small surface area that heat dissipation from the package is lower than for a larger package, although a benefit from the thinness is that there is a very short thermal path between the chip and the outside surface of the package.
WO 88/02552 (General Electric Company) discloses a multichip integrated circuit packaging and method in which a polymer overlayer is laminated over the top of a row of semicondcutor chips carried on a substrate and then via openings are formed in the overlayer, which openings accommodate a layer of interconnection metallization which serves to connect various chips and chip pads within the interconnection pads disposed on the chips. The specification does not address the problem of accommodating the external leads of a package to reduce package size.
EP 0178227 (Fujitsu Limited) discloses an integrated circuit semiconductor device formed on a wafer. The specification also does not address the problem of accommodating the external leads of a package to reduce package size.
U.S. Pat. No. 4,283,839 (Westen Electric Co., Inc.) discloses a method of bonding semiconductor devices to carrier tapes in which a carrier tape has a pattern of lead clusters which are bonded to a chip. The specification does not specifically relate to semiconductor packages.
GB 1530216 (National Semiconductor Corporation) discloses thermal compression gang bonding of interconnect leads to semiconductive devices and terminal structures. GB 1529518 (National Semiconductor Corporation) discloses antioxidant coating of copper parts in thermal compression gang bonding of semicondcutor devices. Neither specification addresses the problem of reducing package size.
The present invention aims at least partially to alleviate the above-specified problems of the prior art and aims to provide a package which takes less volume than the known packages and preferably can also provide improved heat dissipation when compared to the prior art.